Since the invention of integrated circuits, the semiconductor industry has experienced continuous rapid growth due to constant improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, allowing more components to be integrated into a given chip area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvements in lithography have resulted in considerable improvements in 2D integrated circuit formation, there are physical limitations to the density that can be achieved in two dimensions. One of these limitations is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.
An additional limitation comes from the significant increase in the number and lengths of interconnections between devices as the number of devices increases. When the number and the lengths of interconnections increase, both circuit RC delay and power consumption increase.
Efforts for resolving the above-discussed limitations include the use of three-dimensional integrated circuits (3DICs) and stacked dies are commonly used. Through-silicon vias (TSVs) are thus used in 3DICs and stacked dies. In this case, TSVs are often used to connect the integrated circuits on a die to the backside of the die. In addition, TSVs are also used to provide short grounding paths for grounding the integrated circuits through the backside of the die, which may be covered by a grounded metallic film.
The conventional formation process of backside TSV connections suffers from drawbacks. Referring to FIG. 1, which illustrates a cross-sectional view of an intermediate stage in the manufacturing of a backside interconnect structure, silicon wafer 100 includes TSVs 102. Silicon wafer 100 is mounted onto carrier wafer 104 through glue 106. Under-bump metallurgy (UBM) 108 is deposited onto silicon wafer 100. Carrier wafer 104 is typically larger than silicon wafer 100; UBM 108 is thus also deposited on carrier wafer 104. Since carrier wafer 104 has beveled areas 110, UBM 108 includes parts deposited on beveled areas 110, and these parts of UBM 108 are prone to scratching and peeling. In the manufacturing processes, the structure shown in FIG. 1 may be clamped or transferred by robots. When the portions of UBM 108 on beveled areas 110 are clamped or touched by clamps or robots, particles may fall off and contaminate the wafers.
Another problem is the difficulty in finding notches. FIG. 2A illustrates a top view of the structure shown in FIG. 1. Notch 112 is formed in silicon wafer 100 for alignment purposes. FIG. 2B illustrates a cross-sectional view of the structure shown in FIG. 2A, wherein the cross-sectional view is taken in a plane crossing line 2B-2B in FIG. 2A. It is noted that UBM 108 is also deposited onto the portion of carrier wafer 104 exposed through notch 112. Since UBM 108 is not transparent, instruments such as photo steppers often cannot find notch 112, and hence cannot perform alignments for the subsequent processes.
To form the backside TSV connection, the structure as shown in FIG. 1 needs to be placed in chambers, and secured by an electrostatic chuck (ESC or E-Chuck). However, carrier wafer 104 is typically formed of glass and cannot be secured on the ESC firmly. This is partially due to the inadequate mobile ions in the glass. A backside interconnect structure and a manufacturing method overcoming the above-discussed problems are thus needed.